In the design of microprocessors, it has generally been desirable to provide fast and low powered operation. One manner of providing a fast adder is providing a tree structure for carry generation which results in a carry propagation delay proportional to log (N), where (N) is the number of bits in the adder. The base for the log is the number of bits being combined at each node in the tree. For example, if two bits are combined at each node in the tree and it is a 16-bit processor, then the propagation delay through the adder is proportional to log.sub.2 (16) which equals 4.
An example of a tree structure for carry generation is provided in "Digital CMOS Circuit Design", by Marco Annaratone, pages 204-209, at page 207 where FIG. 6-34 illustrates an internal cell having a tree structure for carry generation. The equation at page 207 of the above article illustrates that noninverting logic is to be utilized. Also, the tree structure illustrated provides fanout at least as high as five for a 16-bit adder.
Another known Arithmetic Logic Unit, ALU, scheme is disclosed in U.S. Pat. No. 4,559,608. This patent relates to a CMOS ALU and discloses a look ahead carry circuit using inverting logic.
The present invention provides a full function adder. A full function adder adds two input variables A and B plus a carry in and provides the sum and the carry out of the most significant bit. In the description of the invention it will be convenient to refer to various variables which are generally used in reference to adder design and functioning. These commonly used terms are defined as follows: